Fin field effect transistor (FinFET) devices and logic devices must be electrically isolated from each other by a shallow trench isolation (STI) structure. In order to achieve improved isolation, the STI structure has different thickness requirements for the logic devices and for the FinFET devices. In general, the STI structural thickness for the logic devices is required to be relatively large, and the thickness of STI structure between the fins of the FinFET devices can be relatively small. However, in small-sized devices, such as devices of 14 nm technology nodes or below, the transistor density of a semiconductor integrated circuit device may be high, the silicon recess in an N-type metal oxide semiconductor (NMOS) region and the silicon recess in a P-type metal oxide semiconductor (NMOS) region may overlap and cause the STI structure between the logic devices to be etched twice, resulting in a thinner thickness of the STI structure between the logic devices, thereby affecting the isolation performance of the integrated circuit device. As used herein, the term “NSR” refers to the silicon recess in the NMOS region, and the term “PSR” refers to the silicon recess in the PMOS region.
FIG. 1 shows a plan view of a static random access memory (SRAM) device 100, as known in the prior art. The SRAM device 100 includes a first NMOS region 101, a first PMOS region 102, and a second NMOS region 103. The first NMOS region 101 include a transistor PD1 and a transistor PG1. The first PMOS region 102 includes a transistor PU1 and a transistor PU2. The NSR (NMOS silicon recess) in the NMOS region 101 and the PSR (PMOS silicon recess) in the PMOS region 102 overlap in an overlapping region 104. FIG. 2 shows a cross-sectional view taken along the line AA′ of FIG. 1. As shown in FIG. 2, a first isolation region 111 between the first NMOS region 101 and the first PMOS region 102 is a shallow trench isolation (STI), a second isolation region 112 is an STI between the fins of the transistors. Fins 106 and 107 are the respective fins of the transistors PG1 and PD1, a fin 108 is the fin of the transistor PU1. Because of the presence of the overlapping region 104 (not shown in FIG. 2), the first isolation region 111 is etched twice, thereby thinning its thickness, so that, in a subsequent ion implantation, N+/P+ ions may be implanted into the substrate through the first isolation region 111, thereby affecting isolation and performance of the device. Thus, increasing the thickness of the STI between logic devices is becoming an important concern in the semiconductor industry.